A RISC-V system-on-a-chip and an operating system, designed as one machine.
Zeitlos is a work-in-progress SOC and OS built in tandem, giving FPGA computers a responsive graphical environment for running and writing timeless applications.
The project
A whole computer, small enough to read
zeitlos — German, adj. — timeless
Most computers are a stack of things nobody has read end to end: a CPU you cannot see inside, firmware you cannot change, an OS too large to hold in your head. Zeitlos is an attempt at the opposite — a system where the gateware and the operating system live in one repository and are designed together. When the OS needs something the hardware can grow it, and when the hardware offers something the OS can use it immediately.
It runs on Machdyne FPGA computers and other FPGA development boards. You write the image to flash, and the board comes up in a graphical desktop with a dock, movable windows and a terminal.
The core applications turn the system into an extensible multi-window network terminal with scripting and graphics.
Goals
What we aim for
- Timeless applications Software written against a small, stable system. The target is useful timeless applications that still build and still run decades from now.
- Hardware and software as one design The SOC and OS are designed and developed together, so each is built to what the other actually needs. The OS gets exactly the hardware it needs and the SOC remains as simple as possible.
- Complete on its own Flash a board once and it boots to a desktop. Storage and networking are optional.
- Legible from the gate up Verilog for the machine, C for the system, Scheme for scripting it — each layer small enough to follow. The documentation is being written as a book, Timeless Computing, to be shipped with the system.
- Open, and open to work on Open-source, developed in the open, and buildable with an open toolchain on ordinary hardware.
- Responsive Responds quickly and predictably to what you want to do.
Hardware
The SOC
Written in Verilog, targeting ECP5, Artix-7 and GateMate FPGAs.
| CPU | 32-bit RISC-V (PicoRV32 or Zeitlos32) at 48 MHz, rv32im with hardware multiply and divide, plus an instruction cache |
|---|---|
| GPU | Line rasterizer and blitter |
| MTU | Virtual addressing through a Memory Translation Unit |
| Bus | 32-bit Wishbone |
| Memory | SDRAM, PSRAM or SRAM, 1 MB minimum |
| Framebuffer | 640×480, 1 bit per pixel — monochrome in white, green or amber |
| Video | VGA, DVI, DVI over HDMI |
| Audio | 8 channel hardware mixer |
| Storage | MicroSD |
| Network | Ethernet over SPI, and an Ethernet MAC for RMII PHYs |
| Entropy | Ring-oscillator TRNG |
| Input | USB keyboard, optional USB mouse |
| I/O | GPIO, SPI, 16550 UART |
System
The OS
Written in C, with a Scheme interpreter for scripting.
- Pre-emptive multitasking
- Flat memory model, with a virtual address space for each application
- FAT16 and FAT32 filesystems
- Core applications stored in flash
- Object-based interprocess messaging and streaming
- Networking: IP, ARP, ICMP, UDP, DHCP, NTP, TFTP, TCP, HTTPS, telnet and ssh
Memory translation
Zeitlos has no MMU. Instead there is a single virtual address space that is remapped during context switches. The kernel sits at the start of main memory and applications are loaded immediately after it — but every application executes at the same fixed address, 0x8000_0000, which mirrors wherever it actually lives.
The translation base register is set on each context switch, so an application only ever sees its own memory through one address. No need for position-independent code or relocation.
Main memory — physical
Executing at
The kernel is scheduled as task 0 alongside the applications. Only addresses in the 0x8 region are translated, so each application is mirrored to 0x8000_0000 while the kernel runs untranslated where it sits.
Software
Core applications
Written to flash alongside the kernel and started at boot.
| kernel | Kernel and kernel shell (serial console) |
|---|---|
| wm | Window manager and dock |
| net | Networking server |
| repl | Application server and Lisp interpreter, a subset of R4RS Scheme |
| term | Terminal emulator with VT100 emulation, connects to services |
Anything on an sdcard shadows the copy in flash, so a single application can be replaced during development without reflashing the rest. Further demos, apps and games live in the repository.
Contributing
Get involved
Zeitlos is early and moving quickly — the SOC, the kernel, the window manager and the applications are all still being shaped, and there is plenty left to do. Development happens entirely on GitHub.
Porting to a new board, filling in the drivers, writing applications, and especially testing the system is extremely helpful. If you have an unsupported FPGA board and want to run Zeitlos on it, please open an issue.
Build instructions, the current list of supported boards and the documentation all live in the repository, where they stay up to date with the code.